CCF: SHF Small: Coping with the Slowing of Dennard's Scaling

CCF：SHF Small：应对 Dennard 缩放速度放缓

• 批准号: 1218473
• 负责人: T Vijaykumar
• 金额: $ 10万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-07-15 至 2014-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1218473&HistoricalAwards=false
• 关键词: CCF; SHF; Small; Coping; Slowing

Dennard's scaling, which governs the growth of power, voltage and frequency of CMOS integrated chips, has been as instrumental as Moore's law in enabling the exponential growth of the number of active transistors on a chip. Unfortunately, the recent slowing down of Dennard's scaling of the supply voltage in future multicores may result in dark silicon where an increasing number of cores must be kept powered down due to lack of power. One alternative is to improve power efficiency by customizing the cores for specific functionalities. While the dark silicon option obviously degrades performance, the customization option puts multicores on a potentially arduous path of increased effort for hardware design, verification, and test, and degraded programmability. The challenge that architects face is to design around the reality of the slowing of Dennard's scaling while avoiding either of the two harsh consequences (dark silicon, or the increased cost/effort of customized core design).This project addresses the above challenge by pursuing an alternative, gentle (i.e., non-arduous) path for multicore scaling, while remaining within the power envelope imposed by the slowing of Dennard's scaling. The design employs successive frequency unscaling, where all the cores are kept powered and run at successively slower clocks every generation to stay within the power budget. An analytical model (developed as part of this project) for the performance of systems with and without successive frequency unscaling makes the surprising prediction that despite considerably slower clocks in later generations (e.g., sub-GHz), successive frequency unscaling would exceed the dark silicon performance limit. The key research goal of this project is to validate the predictions of the model with real applications and detailed system simulation. Validating an alternative, gentle path for multicore scaling has the potential to offer significant benefits for the microprocessor and computer industry. Beyond the research impacts, the project's integration of education components in both graduate and undergraduate curricula helps expand its educational impact.

登纳德缩放比例控制着 CMOS 集成芯片的功率、电压和频率的增长，它与摩尔定律一样有助于芯片上有源晶体管数量的指数增长。不幸的是，最近 Dennard 对未来多核电源电压缩放的放缓可能会导致暗硅，其中越来越多的核心由于缺乏电力而必须保持断电状态。一种替代方法是通过定制特定功能的内核来提高能效。虽然暗硅选项明显会降低性能，但定制选项使多核走上了一条潜在的艰巨之路，增加了硬件设计、验证和测试的工作量，并降低了可编程性。架构师面临的挑战是围绕 Dennard 缩放速度放缓的现实进行设计，同时避免两个严重后果中的任何一个（暗硅，或定制核心设计增加的成本/工作量）。该项目通过追求以下目标来解决上述挑战：多核扩展的替代、温和（即不费力）路径，同时保持在 Dennard 扩展减慢所施加的功率范围内。该设计采用连续频率缩放，其中所有内核都保持供电并以逐代较慢的时钟运行，以保持在功率预算之内。 针对具有和不具有连续频率缩放的系统的性能的分析模型（作为该项目的一部分开发）做出了令人惊讶的预测：尽管后代的时钟速度相当慢（例如 sub-GHz），但连续频率缩放将超过暗硅性能限制。该项目的主要研究目标是通过实际应用和详细的系统仿真来验证模型的预测。验证多核扩展的替代、温和路径有可能为微处理器和计算机行业带来显着的好处。除了研究影响之外，该项目将教育内容整合到研究生和本科生课程中，有助于扩大其教育影响。