SHF: Small:Scalable Support for Concurrency in Multicore Systems

SHF：小型：多核系统中并发的可扩展支持

• 批准号: 1217920
• 负责人: Sandhya Dwarkadas
• 金额: $ 40万
• 依托单位: University of Rochester
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-07-01 至 2016-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1217920&HistoricalAwards=false
• 关键词: SHF; Small; Scalable; Support; Concurrency

Processor designs are predicted to continue the many-core trend, often with heterogeneous computational components. While the raw compute power may increase roughly linearly with the core count, unfortunately, realizing the available computational power at the application level remains a challenge. The gap between CPU and memory speeds continues to widen, resulting in the memory system often being unable to feed the computational demands. Parallel application developers and users alike must be aware of the details of the underlying hardware and runtime details in order to extract the most benefit from the system, compromising performance portability. Programmers are also increasingly exploiting concurrency via the use of pre-parallelized libraries, resulting in poor composability. The proposed research aims to address these issues by improving the ease of use, scalability, and energy efficiency of multicore and multiprocessor systems, with impact on environments ranging from smart phone to servers.As part of this research, a "pay-as-you-use" application-adaptive approach is used to develop a novel on-chip memory system. The key observation leveraged is that high-level modular application structure has predictable spatial locality. Rather than use a rigid parameter for the cache line granularity as in current designs, the underlying cache design adapts to match existing access granularity. Additionally, this research aims to develop runtime techniques that map application tasks to hardware compute resources by a) respecting the dependencies across tasks, b) matching task needs with the computational and memory capabilities of the resource, and c) determining the appropriate degree of parallelism at each level to minimize execution time and energy consumption. The new memory system design will improve on-chip storage utilization, eliminate energy wasted in transferring unused bytes of data, and reduce the pressure on off-chip memory bandwidth. The new runtime techniques will improve the ease of use and scalability of computational utilization by the increasingly innovative applications of the future.

处理器设计预计将延续多核趋势，通常采用异构计算组件。虽然原始计算能力可能随核心数量大致线性增加，但不幸的是，在应用程序级别实现可用计算能力仍然是一个挑战。 CPU 和内存速度之间的差距不断扩大，导致内存系统通常无法满足计算需求。并行应用程序开发人员和用户都必须了解底层硬件的详细信息和运行时详细信息，以便从系统中获取最大利益，同时牺牲性能可移植性。程序员还越来越多地通过使用预并行库来利用并发性，从而导致可组合性较差。拟议的研究旨在通过提高多核和多处理器系统的易用性、可扩展性和能源效率来解决这些问题，影响从智能手机到服务器的各种环境。 -use”应用自适应方法用于开发新型片上存储系统。利用的关键观察是高级模块化应用程序结构具有可预测的空间局部性。底层高速缓存设计不是像当前设计中那样对高速缓存行粒度使用严格的参数，而是进行调整以匹配现有的访问粒度。此外，本研究旨在开发运行时技术，通过 a) 尊重任务之间的依赖关系，b) 将任务需求与资源的计算和内存能力相匹配，以及 c) 确定适当的并行度，将应用程序任务映射到硬件计算资源在每个级别上最大限度地减少执行时间和能源消耗。新的内存系统设计将提高片上存储利用率，消除传输未使用数据字节时浪费的能源，并减轻片外内存带宽的压力。新的运行时技术将通过未来日益创新的应用程序来提高计算利用的易用性和可扩展性。