CCF: Small: Improving Trace Based Simulation of On-Chip Networks

CCF：小型：改进片上网络基于跟踪的仿真

• 批准号: 1116897
• 负责人: Venkatesh Akella
• 金额: $ 44.88万
• 依托单位: University of California-Davis
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-07-01 至 2015-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1116897&HistoricalAwards=false
• 关键词: CCF; Small; Improving; Trace; Based

Future computing chips inside mobile devices such as smart phones, and servers used in data centers will contain many processors, memories and specialized functional units, connected by a sophisticated on-chip network. The on-chip network is a critical design element that influences the performance, power consumption, and cost of the chip. Hence, there is a compelling need for tools and techniques to explore the design space of an on-chip network quickly to create networks that are optimized for a given application and/or a market segment. Trace-based simulation is used widely to design and optimize on-chip networks. However, trace-based simulation can result in incorrect and misleading conclusions about network behavior because, a trace does not model the packet injection rate of the application accurately. In this project, the investigators develop techniques to overcome this limitation of trace-based simulation, which allows for rapid design space exploration of on-chip networks with accuracy approaching that of full-system simulation but with simulation time similar to trace-based simulation.Dependencies between packets are inferred by sampling multiple runs of an application on a fully connected network topology with different link latencies. Traces augmented with dependency information, model the packet injection rate of an application more accurately. FPGA-based acceleration is used to collect and analyze traces and a fast multithreaded network simulator that is capable of processing traces augmented with packet dependency information, is developed.The broader impact of the work will be through a validated repository of benchmark traces augmented with the packet dependency information and a multi-threaded network simulator that can be used by the research community to design and optimize on-chip networks with hundreds of processors.

智能手机等移动设备和数据中心使用的服务器内的未来计算芯片将包含许多处理器、存储器和专用功能单元，通过复杂的片上网络连接。片上网络是影响芯片性能、功耗和成本的关键设计元素。因此，迫切需要工具和技术来快速探索片上网络的设计空间，以创建针对给定应用和/或细分市场优化的网络。 基于迹线的仿真广泛用于设计和优化片上网络。然而，基于跟踪的模拟可能会导致有关网络行为的错误和误导性结论，因为跟踪无法准确地对应用程序的数据包注入率进行建模。在这个项目中，研究人员开发了一些技术来克服基于轨迹的仿真的这一局限性，该技术可以快速探索片上网络的设计空间，其精度接近全系统仿真，但仿真时间与基于轨迹的仿真相似。通过在具有不同链路延迟的完全连接的网络拓扑上对应用程序的多次运行进行采样来推断数据包之间的依赖性。使用依赖性信息增强的跟踪可以更准确地对应用程序的数据包注入率进行建模。基于 FPGA 的加速用于收集和分析跟踪，并开发了一个快速多线程网络模拟器，该模拟器能够处理通过数据包依赖性信息增强的跟踪。这项工作的更广泛影响将通过一个经过验证的基准跟踪存储库来增强，该存储库通过数据包依赖性信息和多线程网络模拟器，研究社区可以使用它来设计和优化具有数百个处理器的片上网络。