SHF: Small: Integrated Infrastructures for On-Chip Communication and Power Management in Message-Passing Multicore Processors

SHF：小型：消息传递多核处理器中片上通信和电源管理的集成基础设施

• 批准号: 1018236
• 负责人: Luca Carloni
• 金额: $ 50万
• 依托单位: Columbia University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-08-15 至 2015-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1018236&HistoricalAwards=false
• 关键词: SHF; Small; Integrated; Infrastructures; Chip

While the continued scaling of transistor dimensions enables the integration of an increasing number of processing cores on a single chip, the performance of future multicore processors will be limited by power dissipation and peak temperature constraints. High-performance computing systems will be achievable only through energy-efficient design and energy-aware programming methods. Each core will require dedicated active power and frequency management to make sure that at any given instant it does not waste any energy by operating at a speed higher than what is required by the given task that is executing. Such management requires the introduction of novel on-chip voltage regulation modules, real-time monitoring of the current usage for each voltage domain, as well as detailed awareness of the extent of parallelism achievable for each running application. The PIs will investigate the design and fabrication of a scalable on-chip infrastructure for message-passing multicore processors that integrates support for efficient inter-core communication with programmable fine-grain control mechanisms to regulate independently the processing speed and power dissipation of each core. The proposed infrastructure will consist of a heterogeneous network-on-chip (NoC), a set of voltage and frequency control modules that are distributed on the chip, each next to the controlled core, and a new application programming interface (API). The NoC will be dynamically configured to sustain multiple traffic classes with different quality-of-service requirements. The fine-grained power management will rely on high-Q on-chip magnetic energy storage through the use of magnetic materials in a CMOS post-process fabrication step combined with high-efficiency Buck converters based on pulse-width modulation with hysteric control for fast response times. The API will expose both the inter-core message-passing communication and the voltage/frequency control of each core to the application software programmers. This proposal will allow the PIs to train graduate and undergraduate students in integrated circuit design employing a leading edge CMOS technology and exploiting new magnetic materials as well as in hardware/software co-design of on-chip infrastructures for dynamic power management. Ongoing industrial interactions with leading information-technology and semiconductor companies promise continual relevance of the project and avenues for dissemination.

虽然晶体管尺寸的不断缩小使得能够在单个芯片上集成越来越多的处理核心，但未来多核处理器的性能将受到功耗和峰值温度限制的限制。 高性能计算系统只有通过节能设计和能源感知编程方法才能实现。每个内核都需要专用的有源功率和频率管理，以确保在任何给定时刻，它都不会因运行速度高于正在执行的给定任务所需的速度而浪费任何能量。 这种管理需要引入新颖的片上电压调节模块，实时监控每个电压域的电流使用情况，以及详细了解每个正在运行的应用程序可实现的并行程度。 PI 将研究用于消息传递多核处理器的可扩展片上基础设施的设计和制造，该基础设施将对高效核间通信的支持与可编程细粒度控制机制集成在一起，以独立调节每个核的处理速度和功耗。 拟议的基础设施将包括异构片上网络（NoC）、分布在芯片上的一组电压和频率控制模块（每个模块都靠近受控核心）以及新的应用程序编程接口（API）。 NoC 将进行动态配置，以支持具有不同服务质量要求的多种流量类别。 细粒度电源管理将依靠高 Q 值片上磁能存储，通过在 CMOS 后处理制造步骤中使用磁性材料，结合基于脉冲宽度调制和滞后控制的高效降压转换器，以实现快速响应时间。 API 将向应用软件程序员公开内核间消息传递通信和每个内核的电压/频率控制。 该提案将使 PI 能够对研究生和本科生进行培训，使其掌握采用前沿 CMOS 技术和开发新型磁性材料的集成电路设计，以及用于动态电源管理的片上基础设施的硬件/软件协同设计。 与领先的信息技术和半导体公司持续进行的行业互动保证了该项目和传播途径的持续相关性。