SHF: CSR: Small: Assisted Partitioning and Automated Synthesis of Hybrid Manycore Simulators

SHF：CSR：小型：混合众核模拟器的辅助分区和自动合成

• 批准号: 1017004
• 负责人: David Penry
• 金额: $ 38.87万
• 依托单位: Brigham Young University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-08-01 至 2015-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1017004&HistoricalAwards=false
• 关键词: SHF; CSR; Small; Assisted; Partitioning

Microprocessor designers wish to predict the performance of future microprocessors, evaluate new ideas, and validate new systems. The primary technique they use is software-based simulation. Unfortunately, software-based simulators for manycore microprocessors are slow and will become even slower as the number of cores increases. Slow simulators imply that little exploration of the design space can be done -- few design alternatives are considered and those that are considered are not evaluated thoroughly. Hybrid simulators, which use reconfigurable hardware devices such as Field Programmable Gate Arrays (FPGAs), could accelerate simulators by orders of magnitude, but are themselves very difficult and time-consuming to create; this difficulty arises from the need to first partition the simulator between hardware and software and then design the hardware portions.The goal of this project is to provide tools which allow a designer to easily and quickly create a hybrid simulator from a software-based simulator. The tools will assist the designer to partition the design and then automatically synthesize the hardware portions based upon the selected partitioning. Three different software simulation frameworks -- SystemC, Unisim, and the Liberty Simulation Environment -- will be supported. We target a 100x simulation speed improvement relative to software-based simulators. Achieving this target will require the development of new means to exploit parallel communication and execution between the hardware and software and new means to virtualize the hardware resources. The resulting tools will enable researchers and practitioners to better explore the manycore design space, evaluate new ideas, and validate designs.

微处理器设计人员希望预测未来微处理器的性能、评估新想法并验证新系统。 他们使用的主要技术是基于软件的模拟。不幸的是，用于多核微处理器的基于软件的模拟器速度很慢，并且随着核心数量的增加，速度会变得更慢。缓慢的模拟器意味着对设计空间的探索很少——考虑的设计方案很少，而且考虑到的设计方案也没有得到彻底的评估。 混合模拟器使用可重新配置的硬件设备，例如现场可编程门阵列（FPGA），可以将模拟器加速几个数量级，但其本身的创建非常困难且耗时；这个困难是由于需要首先在硬件和软件之间划分模拟器，然后设计硬件部分。该项目的目标是提供工具，使设计人员能够轻松快速地从基于软件的模拟器创建混合模拟器。 这些工具将帮助设计人员对设计进行分区，然后根据所选分区自动综合硬件部分。 将支持三种不同的软件模拟框架——SystemC、Unisim 和 Liberty 模拟环境。 我们的目标是相对于基于软件的模拟器将模拟速度提高 100 倍。 实现这一目标需要开发新的方法来利用硬件和软件之间的并行通信和执行，以及虚拟化硬件资源的新方法。 由此产生的工具将使研究人员和从业者能够更好地探索众核设计空间、评估新想法并验证设计。