CSR: Small: Scalable Effort Design: Exploiting Algorithmic Resilience for Energy Efficiency

CSR：小：可扩展的工作设计：利用算法弹性来提高能源效率

• 批准号: 1018621
• 负责人: Anand Raghunathan
• 金额: $ 49.9万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1018621&HistoricalAwards=false
• 关键词: CSR; Small; Scalable; Effort; Design

The design processes used to convert algorithms to hardware implementations have obeyed the axiom that the specification and implementation need to be equivalent in a Boolean or numerical sense. However, algorithms from several interesting application domains exhibit the property of ?inherent resilience?, thereby offering entirely new avenues for performance and power optimization by relaxing the requirement of an exact equivalent implementation.We explore scalable effort hardware design as an approach to tap the reservoir of inherent resilience and translate it into highly efficient hardware implementations. We identify mechanisms at each level of design abstraction (circuit, micro-architecture and algorithm) that can be used to vary the computational effort expended towards generation of the correct (exact) result, and expose them as control knobs in the implementation to achieve improved energy efficiency. Fully exploiting the potential of algorithmic resilience requires synergistic cross-layer optimization of scaling mechanisms at different levels of design abstraction. We investigate the nature of the tradeoffs that are possible through cross-layer optimization of scaling mechanisms, and develop techniques to determine the optimal operating point (in terms of the different scaling mechanisms) that maximizes performance or energy efficiency for any given level of output quality.The proposed research will develop new design approaches that can enable unprecedented levels of performance and energy efficiency in hardware implementations of emerging applications such as recognition and mining. We will disseminate our results through publications, release of open source designs, integration into VLSI Design and System-on-Chip course material, and through Purdue?s nanoHub.

用于将算法转换为硬件实现的设计过程遵循这样的公理：规范和实现在布尔或数值意义上需要等效。然而，来自几个有趣的应用领域的算法表现出“固有弹性”的特性，从而通过放宽精确等效实现的要求，为性能和功耗优化提供了全新的途径。我们探索可扩展工作硬件设计作为挖掘水库的方法固有的弹性并将其转化为高效的硬件实现。我们确定了每个设计抽象级别（电路、微架构和算法）的机制，这些机制可用于改变生成正确（精确）结果所需的计算工作量，并将它们作为实现中的控制旋钮公开，以实现改进能源效率。充分发挥算法弹性的潜力需要在不同设计抽象级别对扩展机制进行协同跨层优化。我们研究通过扩展机制的跨层优化可能进行的权衡的本质，并开发技术来确定最佳工作点（就不同的扩展机制而言），从而在任何给定的输出质量水平下最大化性能或能源效率拟议的研究将开发新的设计方法，可以在识别和挖掘等新兴应用的硬件实现中实现前所未有的性能和能源效率水平。我们将通过出版物、发布开源设计、集成到 VLSI 设计和片上系统课程材料以及普渡大学的 nanoHub 来传播我们的成果。