Towards A Theory of Communication With Sloppy Analog-to-Digital Conversion: A Framework for Low-Cost Gigabit wireless

走向一种具有马虎模数转换的通信理论：低成本千兆位无线框架

• 批准号: 0729222
• 负责人: Upamanyu Madhow
• 金额: $ 30万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-10-01 至 2010-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0729222&HistoricalAwards=false
• 关键词: Towards; Theory; Communication; Sloppy; Analog

The economies of scale of cellular and WiFi networks are enabled by low-cost integrated circuit implementations of sophisticated digital signal processing (DSP) algorithms in wireless communication transceivers. An implicit assumption in this approach is that analog received signals can be converted to a reasonably faithful digital representation, an assumption that breaks down as link speeds increase to the point that high-precision analog-to-digital conversion (ADC) becomes too costly and power-hungry. This project involves the design of wireless networks in the latter regime: the goal is to design low-cost links operating at multiGigabit speeds (i.e., more than an order of magnitude faster than WiFi), exploiting large swaths of unlicensed spectrum in the 3-10 GHz band and the 60 GHz band. The research rethinks communication transceiver design, with the starting assumption that high-speed ADCs are ``sloppy.'' The research involves obtaining fundamental performance benchmarks using information theory, and devising DSP algorithms that achieve these performance benchmarks. The ultimate objective is to enable a quantum leap in the speed of wireless networks for the home and enterprise, while preserving the economies of scale associated with low-cost silicon implementations.While conventional systems use 6-12 bits of ADC precision, this research considers the design of communication systems for low-resolution (1-4 bits) ADC, including Shannon theoretic benchmarks and algorithms for synchronization and equalization. Since high-speed digital-to-analog conversion is easier than ADC, precoding strategies which move complexity to the transmitter are investigated. The use of time-interleaved ADCs to attain higher precision, and hence higher dynamic range, is considered for both singlecarrier and multicarrier systems. The approach is to design receiver algorithms that jointly address mismatch between the component ADCs and the channel dispersion.

细胞和WiFi网络规模的经济体是通过无线通信收发器中复杂数字信号处理（DSP）算法的低成本集成电路实现来实现的。 这种方法中的一个隐含假设是，模拟接收的信号可以转换为合理忠实的数字表示，这一假设会随着链接速度的增加而分解，直到高精度模拟到数字转换（ADC）变得太昂贵，而且耗电。 该项目涉及后一种策略中无线网络的设计：目标是设计以多智能速度运行的低成本链接（即，比WiFi快的速度超过一个数量级），利用了3--的大量未经许可的频谱。 10 GHz频段和60 GHz频段。 该研究重新考虑了通信收发器设计，并以高速ADC为``草率''的首个假设。该研究涉及使用信息理论获得基本性能基准，并设计DSP算法以实现这些性能基准。最终目标是在家庭和企业的无线网络速度方面实现量子飞跃，同时保留与低成本硅实施相关的规模经济。尽管常规系统使用6-12位ADC精度，但此研究认为低分辨率（1-4位）ADC的通信系统的设计，包括香农理论基准和算法，用于同步和均衡。 由于高速数字到分析转换比ADC更容易，因此研究了将复杂性转移到发射器的预编码策略。 对于单载波和多载波系统，考虑使用时间间隔的ADC来达到更高的精度，因此可以使用更高的动态范围。 该方法是设计接收器算法，该算法共同解决了组件ADC与通道分散之间的不匹配。