Communication and Synchronization Mechanisms for Emerging Multi-Core Processors

新兴多核处理器的通信和同步机制

• 批准号: 0702505
• 负责人: Sandhya Dwarkadas
• 金额: --
• 依托单位: University of Rochester
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-09-01 至 2010-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702505&HistoricalAwards=false
• 关键词: Communication; Synchronization; Mechanisms; Emerging; Multi

CCF-CPA: Communication and Synchronization Mechanisms for Emerging Multi-Core ProcessorsSandhya Dwarkadas and Michael L. ScottMarch 2007As a result of increasing chip density and power limitations, explicit hardware parallelism will soon dominate the computing spectrum, with multicore chips replacing uniprocessors throughout the desktop andlaptop markets. If these chips are to be used effectively, new programming models must ease the task of writing multithreaded code. These models must in turn be supported by architectural mechanisms thatminimize the cost of data communication and synchronization.The sponsored research addresses the challenge of mainstream parallelism using a combined hardware-software approach. The key idea is to identify common time-critical operations, across a variety of applications and programming models, that might be accelerated or simplified by new architectural mechanisms, and then to design those mechanisms in as general a fashion as possible. By leaving policy tosoftware whenever possible, this strategy aims to maximize opportunities for adaptive and application-specific protocols that increase scalability. Candidate hardware mechanisms include alert-on-update, which leverages cache coherence for fast event-based communication; programmable data isolation, which allows a processor to hide local writes for speculation and transactions; and adaptive cooperative caching, which re-engineers the on-chip coherence protocol to accommodate different patterns of data sharing and to communicate values efficiently between cores. These mechanisms will be studied mainly at the hardware level, but system software will also be developed to support new programming models (transactions, speculation) and to enable detailed evaluation of performance and programmability.Through better parallel programming models and efficient implementations, the sponsored research aims to continue the computing revolution over the course of the coming decade. By enabling the effective use of larger numbers of simpler cores, it also addresses the critical need to reduce energy consumption in mainstream processors. Driving applications will be drawn from multiple sources, including collaborative efforts with University colleagues in Biology, Astrophysics, and Chemistry; department colleagues in Artificial Intelligence and Internet services; and local and remote colleagues in data mining. Programming models and tasks will include transactional computing, speculative execution, and performance and correctness debugging.

CCF-CPA：新兴多核处理器的通信和同步机制Sandhya Dwarkadas 和 Michael L. Scott 2007 年 3 月 由于芯片密度和功率限制的增加，显式硬件并行性将很快在计算领域占据主导地位，多核芯片将取代整个台式机和笔记本电脑中的单处理器市场。 如果要有效地使用这些芯片，新的编程模型必须减轻编写多线程代码的任务。这些模型反过来必须得到架构机制的支持，从而最大限度地降低数据通信和同步的成本。赞助的研究使用硬件-软件相结合的方法解决了主流并行性的挑战。 关键思想是识别跨各种应用程序和编程模型的常见时间关键操作，这些操作可以通过新的架构机制来加速或简化，然后以尽可能通用的方式设计这些机制。 通过尽可能将策略留给软件，该策略旨在最大限度地提高自适应和特定于应用程序的协议的机会，从而提高可扩展性。 候选硬件机制包括更新警报，它利用缓存一致性来实现基于事件的快速通信；可编程数据隔离，允许处理器隐藏推测和事务的本地写入；自适应协作缓存，它重新设计了片上一致性协议，以适应不同的数据共享模式，并在内核之间有效地传递值。 这些机制将主要在硬件级别进行研究，但也将开发系统软件以支持新的编程模型（事务、推测）并实现对性能和可编程性的详细评估。通过更好的并行编程模型和高效的实现，赞助的研究旨在在未来十年继续推动计算革命。 通过有效利用大量更简单的内核，它还满足了降低主流处理器能耗的迫切需求。驱动应用程序将来自多个来源，包括与大学生物学、天体物理学和化学领域同事的合作；人工智能和互联网服务部门的同事；以及数据挖掘方面的本地和远程同事。 编程模型和任务将包括事务计算、推测执行以及性能和正确性调试。