NANOWIRE CROSSBAR SWITCH ESD PROTECTION MECHANISM AND CIRCUIT

纳米线交叉开关ESD保护机制和电路

• 批准号: 0701687
• 负责人: Albert Wang
• 金额: $ 27万
• 依托单位: Illinois Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-05-01 至 2008-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0701687&HistoricalAwards=false
• 关键词: NANOWIRE; CROSSBAR; SWITCH; ESD; PROTECTION

The objective of this research is to develop non-traditional Electrostatic Discharge (ESD) protection mechanisms and structures, using novel nanowire crossbar array and nano mechanical switch mechanisms, for nanoscale integrated circuits (IC). The approach is to investigate new nanowire switching ESD discharging mechanism, to fabricate and characterize nano crossbar switch arrays, to explore CMOS-compatible fabrication flow and to develop new modeling techniques.Intellectual Merits: ESD failure is the most devastating IC reliability problem in sub-100nm regime that causes the industry billions of dollars annually. On-chip ESD protection is hence required to protect ICs against ESD damage. ESD failure and protection involves very complex multi-coupling effects. As IC technologies continue to shrink, ESD-induced leakage and mis-triggering effect at GHz operation, inherent to its traditional transistor-type protection mechanism, become intolerable. It is hence imperative to develop novel ESD protection mechanisms and structures. This project is to develop completely new nanowire crossbar array and nano mechanical switch based ESD protection mechanisms and structures, which intends to replace the decade-long traditional ESD protection mechanism, therefore to eliminate the ESD-induced leakage and mis-triggering problems. Broader Impacts: Success of this project will deliver the first nanowire crossbar array and nano mechanical switch ESD protection mechanisms and structures for next generation IC technologies at nanoscale. The new ESD protection solutions are critical to finally resolving the grand IC reliability challenge at nano nodes. NSF support of this research enables the proposed international-academia-industry collaboration activities that greatly benefit American students, the semiconductor industry, the academia and the American society.

本研究的目的是利用新型纳米线交叉阵列和纳米机械开关机制，为纳米级集成电路（IC）开发非传统静电放电（ESD）保护机制和结构。该方法旨在研究新的纳米线开关 ESD 放电机制，制造和表征纳米交叉开关阵列，探索 CMOS 兼容的制造流程并开发新的建模技术。 100nm 体系每年为该行业带来数十亿美元的收入。因此需要片上 ESD 保护来保护 IC 免受 ESD 损坏。 ESD 故障和保护涉及非常复杂的多重耦合效应。随着 IC 技术不断缩小，传统晶体管型保护机制所固有的 ESD 引起的泄漏和误触发效应在 GHz 操作下变得难以忍受。因此，开发新颖的ESD保护机制和结构势在必行。该项目旨在开发全新的基于纳米线交叉阵列和纳米机械开关的ESD保护机制和结构，旨在取代长达十年的传统ESD保护机制，从而消除ESD引起的泄漏和误触发问题。更广泛的影响：该项目的成功将为下一代纳米级 IC 技术提供第一个纳米线交叉阵列和纳米机械开关 ESD 保护机制和结构。新的 ESD 保护解决方案对于最终解决纳米节点 IC 可靠性的重大挑战至关重要。 NSF 对这项研究的支持使得拟议的国际学术界和工业界合作活动成为可能，极大地造福于美国学生、半导体行业、学术界和美国社会。