NSF CCF-CPA: Reliability in the Face of Variability under Nanoscale Technology Scaling

NSF CCF-CPA：纳米技术扩展下面对可变性的可靠性

• 批准号: 0702344
• 负责人: David Brooks
• 金额: $ 45万
• 依托单位: Harvard University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-07-01 至 2012-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702344&HistoricalAwards=false
• 关键词: NSF; CCF; CPA; Reliability; Face

Technology scaling has enabled tremendous growth in the integrated circuits (IC) industry over the past few decades. While Moore's Law seems to be going strong, fine line widths in current and future nanoscale technologies (e.g., 45nm and below) present several obstacles that have the potential to limit continued device scaling, curtail frequency improvements, and cause increased leakage power in future microprocessors. To make matters worse, voltage and temperature fluctuations arise from increasing power dissipation and techniques that attempt to reduce power. The combined impact of these variations forces designers to incorporate larger amounts of design margins in order to guarantee reliable operation. This proposal seeks to address the issue of variability in a cooperative fashion at both the circuit and architecture levels to ensure reliable operation of next-generation computing systems.This proposal outlines work along three main research thrusts. The first thrust investigates circuit and architectural solutions to deal with the growing concern over reliability of on-chip memories and obtaining consistent levels of performance for each manufactured chip. These concerns arise from variations when manufacturing transistors in aggressively-scaled technologies. The second thrust seeks to minimize the aforementioned margins in critical parts of a chip via flexible circuit and architecture configurations that can accommodate variations. The third thrust leverages the first two efforts to understand the impact of variability and to offer guidelines for variability-tolerant chip-multiprocessor designs.

在过去的几十年中，技术扩展已使综合电路（IC）行业的巨大增长。 虽然摩尔定律似乎在强劲，但在当前和未来的纳米级技术（例如45nm及以下）中的细线宽度却呈现出几个障碍，这些障碍有可能限制持续的设备缩放，减少降低频率的改善，并在未来的微处理器中提高泄漏功率。 更糟糕的是，电压和温度波动是由于耗能的增加和试图降低功率的技术而引起的。这些变体的综合影响迫使设计师合并大量的设计余量，以保证可靠的操作。 该提案旨在以合作方式和建筑水平的合作方式解决可变性问题，以确保下一代计算系统的可靠操作。该提案概述了沿三个主要研究推力的工作。第一个推力研究了电路和建筑解决方案，以应对对芯片记忆的可靠性日益关注的关注，并为每个制造的芯片获得一致的性能水平。 这些担忧是由于在积极缩放技术中制造晶体管时的变化。第二个推力旨在通过柔性电路和可以适应变化的构建配置来最大程度地减少芯片关键部分中上述边缘的最低限制。第三个推力利用了前两项努力，以了解变异性的影响，并为易变性的芯片 - 属性处理器设计提供指南。