Programmable Architectures for Low Density Parity Check Codes

低密度奇偶校验码的可编程架构

• 批准号: 0429154
• 负责人: Venkatesh Akella
• 金额: --
• 依托单位: University of California-Davis
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-09-01 至 2009-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0429154&HistoricalAwards=false
• 关键词: Programmable; Architectures; Low; Density; Parity

AbstractProgrammable Architectures for Low Density Parity Check CodesVenkatesh Akella Shu LinUniversity of California University of CaliforniaLow-density parity check (LDPC) codes are an important class of error control codes that have superior performance and are gaining widespread use in a diverse range of applications from satellite and space communication to magnetic recording to high data rate optical networks based on optical CDMA. The wide range of applications imply a broad range of requirements in terms of data rates, bit and block error rates, performance, decoding speed and power consumption. This necessitates a systematic methodology to design good LDPC codes and hardware/software platforms to implement them efficiently.Specifically we argue that we need codes and architectures that can (dynamically) adapt to time-varying fluctuations in the physical channel (due to fading, interference etc.) and to the resource constraints of the sender or receiver. The latter is especially important in power critical applications like satellite or space communications. Existing code construction methods and hardware architectures for LDPC codes are typically tailored for one specific code and hence are not capable of adaptation. The goal of this proposal is to address this problem. We propose a systematic methodology for generating a large family of related LDPC codes and a single programmable hardware architecture to encode and decode them efficiently for a varietyof resource and performance constraints. We propose a joint framework for code construction, implementation platform design and methods for optimizing the implementation of the codes on the platform. We propose to investigate runtime selection of appropriate codes and encoding/decoding algorithms based on the resource constraints. The main resource we will be interested in is power consumption of the encoder and decoder.The intellectual merit of the proposed research is two fold. First, we propose to study the trade-offsbetween the rate, decoding complexity both in terms of energy and time and error performance. Second, we target programmable architectures that are suitable for optical networking applications, which require very low bit-error rate and decoding rates in tens of gigabits per second. This will push the limit of programmable architectures and yield new insights into high-speed on-chip programmable interconnection network design.The broader impact of the proposed research would be in the area of reconfigurable VLSI fabrics. Aswe move into process technologies below 65 nanometers, building ASICs (application-specific integrated circuits) is increasingly less viable due to the problems of timing closure and the design cost and design cycle time. There is an immediate need for a new kind of computing fabric that can replace ASICs. The proposed research will be addressing this problem indirectly. Given that efficient interconnect design is the key challenge in high-speed LDPC decoding, if we can come up with an energy efficient FPGA-like VLSI fabric that can support very high data rates for LDPC decoding, then it is likely that, that fabric can be used for other high performance applications that have demanding interconnect requirements.

摘要：低密度奇偶校验码的可编程架构Venkatesh Akella Shu Lin 加州大学 加州大学 低密度奇偶校验（LDPC）码是一类重要的错误控制码，具有卓越的性能，并在卫星和卫星等各种应用中得到广泛应用。空间通信、磁记录、基于光 CDMA 的高数据速率光网络。广泛的应用意味着在数据速率、比特和块错误率、性能、解码速度和功耗方面的广泛要求。这就需要一种系统的方法来设计良好的 LDPC 代码和硬件/软件平台来有效地实现它们。具体来说，我们认为我们需要能够（动态）适应物理信道中随时间变化的波动（由于衰落、干扰）的代码和架构。等）以及发送者或接收者的资源限制。后者在卫星或太空通信等电力关键应用中尤其重要。现有的LDPC码的码构造方法和硬件架构通常是针对一种特定码而定制的，因此不能够适应。本提案的目的就是解决这个问题。我们提出了一种生成大量相关 LDPC 码的系统方法，以及一个单一的可编程硬件架构，可以针对各种资源和性能限制对其进行有效编码和解码。我们提出了代码构建、实施平台设计的联合框架以及优化平台上代码实施的方法。我们建议根据资源限制研究适当代码和编码/解码算法的运行时选择。我们感兴趣的主要资源是编码器和解码器的功耗。所提出的研究的智力价值有两个方面。首先，我们建议研究速率、解码复杂度（在能量和时间方面）以及错误性能之间的权衡。其次，我们的目标是适合光网络应用的可编程架构，这些应用需要非常低的误码率和每秒数十吉比特的解码速率。这将突破可编程架构的极限，并为高速片上可编程互连网络设计带来新的见解。拟议研究的更广泛影响将出现在可重构 VLSI 结构领域。随着我们转向 65 纳米以下的工艺技术，由于时序收敛以及设计成本和设计周期时间的问题，构建 ASIC（专用集成电路）变得越来越不可行。迫切需要一种可以取代 ASIC 的新型计算结构。拟议的研究将间接解决这个问题。鉴于高效互连设计是高速 LDPC 解码的关键挑战，如果我们能够提出一种节能的类似 FPGA 的 VLSI 结构，可以支持非常高的 LDPC 解码数据速率，那么该结构很可能可以可用于具有严格互连要求的其他高性能应用。