ITR: Architectures and Design Methodologies for Secure Low-Power Embedded Systems

ITR：安全低功耗嵌入式系统的架构和设计方法

• 批准号: 0326372
• 负责人: Ruby Lee
• 金额: $ 52.5万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-01 至 2007-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0326372&HistoricalAwards=false
• 关键词: ITR; Architectures; Design; Methodologies; Secure

Embedded systems, for example in information appliances and networkedsensors, face some of the most demanding security concerns - they are resourceconstrained while frequently needing to handle sensitive information inphysically insecure environments. Security processing can easily overwhelm thelimited computation and memory resources of embedded processors, especially withthe escalation in the amount of data to be processed and the data rates ofhigh-speed networks. This "performance gap" is compounded by the "battery gap",which is the disparity between energy requirements and slow improvements inbattery technology, for secure low-power embedded systems. This project is an inter-disciplinary study of several core technologiesthat will enable the design of secure, low-power embedded systems. It spans thefields of security, cryptographic algorithms, embedded processor architecture,computer arithmetic, low power design, and enabling design methodologies andtools. It addresses the performance, energy and security requirements, andtheir tradeoffs, in embedded processors and systems. The research goals includea comprehensive analysis of the performance requirements and power consumptionfor security in embedded systems. The project is developing efficient architecturesfor security processing in low-power embedded systems, including configurablesecurity modules for system-on-chip designs, and architectural guidelines fortiny cryptographic processors for embedded systems. The performance, power andsecurity tradeoffs based on customizations at the protocol, cryptographicalgorithm, and hardware and software implementation levels are studied. Designmethodology and tools include processor design tools to facilitate the design ofnew security processing architectures based on open frameworks such as the PLX(hosted at Princeton) and SimpleScalar toolkits. The project exploresdomain-specific design methodologies that jointly co-design security protocolsand processing architectures to meet the required security, performance andpower priorities and constraints. The research enables the design of embedded systems with higher levels ofsecurity, while achieving an order of magnitude or more in performance andbattery life, compared to conventional approaches. Broad security impacts are expected for embedded system design, in addition to impact for future research and education. Results are disseminated to industry through the Princeton Architecture Lab for Multimedia and Security (PALMS) and the NJCST Center for Embedded System-on-a-Chip Design. The research results are being woven into graduate and undergraduate courses.

嵌入式系统（例如信息设备和网络传感器中的嵌入式系统）面临着一些最严格的安全问题 - 它们资源有限，同时经常需要在物理不安全的环境中处理敏感信息。安全处理很容易超出嵌入式处理器有限的计算和内存资源，尤其是随着要处理的数据量和高速网络的数据速率的不断增加。这种“性能差距”与“电池差距”进一步加剧，“电池差距”是安全低功耗嵌入式系统的能源需求与电池技术缓慢改进之间的差距。 该项目是对多项核心技术的跨学科研究，可实现安全、低功耗嵌入式系统的设计。 它涵盖安全、加密算法、嵌入式处理器架构、计算机算术、低功耗设计以及支持设计方法和工具等领域。 它解决了嵌入式处理器和系统中的性能、能源和安全要求及其权衡。研究目标包括全面分析嵌入式系统安全性的性能要求和功耗。该项目正在开发低功耗嵌入式系统安全处理的高效架构，包括用于片上系统设计的可配置安全模块，以及用于嵌入式系统的微型密码处理器的架构指南。 研究了基于协议、加密算法以及硬件和软件实现级别的定制的性能、功耗和安全性权衡。 设计方法和工具包括处理器设计工具，以促进基于开放框架（例如 PLX（在普林斯顿托管）和 SimpleScalar 工具包）设计新的安全处理架构。该项目探索特定领域的设计方法，共同设计安全协议和处理架构，以满足所需的安全、性能和功耗优先级和约束。 与传统方法相比，该研究能够设计出具有更高安全级别的嵌入式系统，同时在性能和电池寿命方面实现一个数量级或更多。 除了对未来研究和教育的影响之外，预计嵌入式系统设计也会产生广泛的安全影响。 结果通过普林斯顿多媒体与安全架构实验室 (PALMS) 和 NJCST 嵌入式片上系统设计中心向业界传播。研究成果正在融入研究生和本科生课程。