ITR: An Optimizing Compiler for Languages with Programmable Memory Models

ITR：具有可编程内存模型的语言的优化编译器

• 批准号: 0081265
• 负责人: David Padua
• 金额: $ 49万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-09-01 至 2004-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0081265&HistoricalAwards=false
• 关键词: ITR; Optimizing; Compiler; Languages; Programmable; ITR; Optimizing; Compiler; Languages; Programmable

The memory model for a programming language specifiesthe relationship between the order in which data accessesappear in a program and the order seen during execution bythe different program components With the advent of parallelprogramming environments like Posix threads, Java, and OpenMP, multi-threaded explicitly parallel programs have become much morefrequent. This increases the need for memory models thatare easy to understand and efficient so that correct pro-grams can be developed and still give good performance.Unfortunately, the usability of memory models, their impacton performance, and the compiler technology needed to per-form optimizations of parallel programs are poorly under-stood. The result is that current memory models tend tofavor performance over usability by restricting the programsthat can be written with them, or by being difficult tounderstand. The objective of this project is to study com-piler techniques to optimize explicitly parallel programs byusing optimizations and analysis algorithms structured tohandle a broad class of consistency models. The techniquesstudied will be implemented in a compiler that will serveas a testbed for prototyping and studying programminglanguage memory models and for studying the optimizationand analysis of explicitly parallel programs.

编程语言指定的内存模型在程序中的数据访问访问的顺序与在执行过程中由不同的程序组件所看到的顺序访问的顺序，并随行编程环境出现了POSIX线程，Java和OpenMP（OpenSMP），多线读取的明确并行程序变得更加频繁。这增加了对易于理解和高效的内存模型的需求，因此可以开发正确的pro-grams并仍然具有良好的性能。结果是，当前的内存模型可以通过限制可以与它们编写的程序或难以通过Tounderstand编写的程序来倾向于性能。该项目的目的是研究COM-PILER技术，以通过优化和分析算法结构构成广泛的一致性模型来优化明确的并行程序。该技术将在编译器中实施，该编译器将为原型制作和研究编程语言记忆模型，并研究明确并行程序的优化和分析。