ITR: An Optimizing Compiler for Languages with Programmable Memory Models

ITR：具有可编程内存模型的语言的优化编译器

• 批准号: 0081265
• 负责人: David Padua
• 金额: $ 49万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-09-01 至 2004-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0081265&HistoricalAwards=false
• 关键词: ITR; Optimizing; Compiler; Languages; Programmable

The memory model for a programming language specifiesthe relationship between the order in which data accessesappear in a program and the order seen during execution bythe different program components With the advent of parallelprogramming environments like Posix threads, Java, and OpenMP, multi-threaded explicitly parallel programs have become much morefrequent. This increases the need for memory models thatare easy to understand and efficient so that correct pro-grams can be developed and still give good performance.Unfortunately, the usability of memory models, their impacton performance, and the compiler technology needed to per-form optimizations of parallel programs are poorly under-stood. The result is that current memory models tend tofavor performance over usability by restricting the programsthat can be written with them, or by being difficult tounderstand. The objective of this project is to study com-piler techniques to optimize explicitly parallel programs byusing optimizations and analysis algorithms structured tohandle a broad class of consistency models. The techniquesstudied will be implemented in a compiler that will serveas a testbed for prototyping and studying programminglanguage memory models and for studying the optimizationand analysis of explicitly parallel programs.

编程语言的内存模型指定了数据访问在程序中出现的顺序与不同程序组件执行期间看到的顺序之间的关系随着 Posix 线程、Java 和 OpenMP 等并行编程环境的出现，多线程显式并行程序已经变得更加频繁。这增加了对易于理解和高效的内存模型的需求，以便可以开发正确的程序并仍然提供良好的性能。不幸的是，内存模型的可用性、它们对性能的影响以及执行形式优化所需的编译器技术对并行程序的了解还很有限。结果是，当前的内存模型通过限制可以用它们编写的程序或难以理解而倾向于注重性能而不是可用性。该项目的目标是研究编译器技术，通过使用优化和分析算法来优化显式并行程序，以处理广泛的一致性模型。所研究的技术将在编译器中实现，该编译器将作为原型设计和研究编程语言内存模型以及研究显式并行程序的优化和分析的测试平台。