Adaptive Balanced Computing Architecture

自适应平衡计算架构

• 批准号: 9900601
• 负责人: Arun Somani
• 金额: $ 35万
• 依托单位: Iowa State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-09-15 至 2003-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9900601&HistoricalAwards=false
• 关键词: Adaptive; Balanced; Computing; Architecture

Applications, such as multimedia processing, digital signal, image and vision processing, and scientific computing, generate computation tasks that are structured and repetitive exhibiting varying degree of instruction-level parallelism (ILP). Moreover, the demands to compute certain functions and theirresource needs vary with applications and time. The overall goal of this project is to develop and use novel ideas such as reconfigurable functional units (FUs), cache memory, and reconfigurable bus architectures to achieve balanced computing, i.e. match the computing bandwidth to the memory bandwidth. The research will address issues in designing architectures that allow reconfiguration of resources to make the following architecture level parameters dynamically variable: number and types of FUs, amount of on-chip register and cache memory, an ability to trade the on-chip memory resources with the numberof FUs dynamically, and the interconnectivity between these units. A processor core with reconfigurable logic blocks to make the architecture adaptive to the applications' computing and memory bandwidth needs will be developed. Effects of integrating reconfiguration schemes into the on-chip FUs and cache memorieson a processor chip will also be studied and evaluated. A high-level design for the ABC (Adaptive Balanced Computing) architecture will be developed and analyzed. It is expected that the research results will significantly improve the efficiency of computation.

应用程序，例如多媒体处理，数字信号，图像和视觉处理以及科学计算，生成结构化和重复性的计算任务，表现出不同程度的教学级并行性（ILP）。此外，计算某些功能及其资源需求的需求随应用和时间而变化。该项目的总体目标是开发和使用新颖的想法，例如可重构功能单元（FUS），缓存内存和可重新配置的总线体系结构，以实现平衡的计算，即将计算带宽匹配到内存带宽。该研究将解决设计架构的问题，这些架构允许重新配置资源以使以下体系结构级别参数动态变化：FUS的数量和类型，片上寄存器和缓存内存的数量，可以动态的芯片内存资源与FUS数量交易的能力以及这些单元之间的互连性。具有可重构逻辑块的处理器核心将开发适应应用程序计算和内存带宽需求的体系结构。还将研究和评估将重新配置方案整合到片上FUS和缓存备件中的影响。 将开发和分析ABC（自适应平衡计算）体系结构的高级设计。预计研究结果将显着提高计算效率。