Adaptive Balanced Computing Architecture

自适应平衡计算架构

• 批准号: 9900601
• 负责人: Arun Somani
• 金额: $ 35万
• 依托单位: Iowa State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-09-15 至 2003-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9900601&HistoricalAwards=false
• 关键词: Adaptive; Balanced; Computing; Architecture

Applications, such as multimedia processing, digital signal, image and vision processing, and scientific computing, generate computation tasks that are structured and repetitive exhibiting varying degree of instruction-level parallelism (ILP). Moreover, the demands to compute certain functions and theirresource needs vary with applications and time. The overall goal of this project is to develop and use novel ideas such as reconfigurable functional units (FUs), cache memory, and reconfigurable bus architectures to achieve balanced computing, i.e. match the computing bandwidth to the memory bandwidth. The research will address issues in designing architectures that allow reconfiguration of resources to make the following architecture level parameters dynamically variable: number and types of FUs, amount of on-chip register and cache memory, an ability to trade the on-chip memory resources with the numberof FUs dynamically, and the interconnectivity between these units. A processor core with reconfigurable logic blocks to make the architecture adaptive to the applications' computing and memory bandwidth needs will be developed. Effects of integrating reconfiguration schemes into the on-chip FUs and cache memorieson a processor chip will also be studied and evaluated. A high-level design for the ABC (Adaptive Balanced Computing) architecture will be developed and analyzed. It is expected that the research results will significantly improve the efficiency of computation.

多媒体处理、数字信号、图像和视觉处理以及科学计算等应用会生成结构化和重复性的计算任务，并表现出不同程度的指令级并行性 (ILP)。此外，计算某些函数的需求及其资源需求随着应用程序和时间的不同而变化。该项目的总体目标是开发和使用可重构功能单元（FU）、高速缓存和可重构总线架构等新颖的想法来实现平衡计算，即将计算带宽与内存带宽相匹配。该研究将解决设计架构中的问题，该架构允许重新配置资源，使以下架构级参数动态变化：FU 的数量和类型、片上寄存器和高速缓存的数量、与片上存储器资源进行交换的能力。 FU 的动态数量以及这些单元之间的互连性。将开发具有可重新配置逻辑块的处理器核心，以使架构适应应用程序的计算和内存带宽需求。还将研究和评估将重新配置方案集成到处理器芯片上的片上 FU 和高速缓冲存储器中的效果。 将开发和分析 ABC（自适应平衡计算）架构的高级设计。预计研究成果将显着提高计算效率。