Automated Synthesis of High Performance Clock Distribution Networks

高性能时钟分配网络的自动综合

• 批准号: 9423886
• 负责人: Eby Friedman
• 金额: $ 19.5万
• 依托单位: University of Rochester
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1995
• 资助国家: 美国
• 起止时间: 1995-07-01 至 1999-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9423886&HistoricalAwards=false
• 关键词: Automated; Synthesis; Performance; Clock; Distribution

This research is on automated synthesis of high speed, highly reliable clock distribution networks. A global clock signal is required in order to control synchronous operations, and it must be distributed to every register at a precise time. A four phase top-down design system for synthesizing buffered clock distribution networks is being investigated. Models of operation which include the effects of process parameter variations on timing are being developed. Scheduling clock skew is done at the behavioral level of the system. The clock distribution algorithms are being included in an integrated synthesis system.

这项研究是关于高速、高度可靠的时钟分配网络的自动综合。 为了控制同步操作，需要全局时钟信号，并且必须在精确的时间将其分配到每个寄存器。 正在研究用于合成缓冲时钟分配网络的四阶段自顶向下设计系统。 正在开发包括工艺参数变化对时序影响的操作模型。 调度时钟偏差是在系统的行为级别完成的。 时钟分配算法被包含在集成综合系统中。