RIA: Integrating Computer-Aided Design and Fault Tolerance for Reconfigurable VLSI/WSI Architectures Design

RIA：集成计算机辅助设计和容错以实现可重构 VLSI/WSI 架构设计

• 批准号: 8908648
• 负责人: Sy-Yen Kuo
• 金额: $ 6万
• 依托单位: University of Arizona
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1989
• 资助国家: 美国
• 起止时间: 1989-06-01 至 1991-11-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8908648&HistoricalAwards=false
• 关键词: RIA; Integrating; Computer; Aided; Design

The objective of this research is to provide an integrated computer- aided design (CAD) environment for the synthesis and evaluation of reconfigurable VLSI (very-large scale integrated) or WSI (wafer-scale integration) concurrent architectures. With the rapid progress of VLSI technology, the chip sizes are to increase substantially, perhaps up to the level of WSI. However, low manufacturing yield has become a problem of increasing significance, especially in WSI where it is unlikely to get a defect-free wafer. Redundancy techniques are being utilized to overcome this difficulty. Substantial yield and reliability improvement in VLSI/WSI parallel architectures can be achieved by a proper integration of the architectural redundancy, fault diagnosis, and reconfiguration techniques. Initial promising results have been obtained on these issues and further investigation is being performed to enhance the reconfigurability of classes of architectures, and performance of diagnosis and reconfiguration algorithms. Moreover, CAD and analysis tools are being developed to assist the computer architect in the synthesis and evaluation of alternative highly parallel designs appropriate for yield and reliability enhancement. The emphasis is on analysis and design of application specific reconfigurable concurrent architectures and reconfiguration algorithms appropriate for WSI.

本研究的目的是提供一个集成的计算机辅助设计（CAD）环境，用于可重构VLSI（超大规模集成）或WSI（晶圆级集成）并发架构的综合和评估。 随着VLSI技术的快速进步，芯片尺寸将大幅增加，甚至可能达到WSI的水平。 然而，低制造良率已成为一个日益重要的问题，特别是在 WSI 中，不太可能获得无缺陷的晶圆。 正在利用冗余技术来克服这一困难。 通过架构冗余、故障诊断和重新配置技术的适当集成，可以实现 VLSI/WSI 并行架构中产量和可靠性的大幅提高。 在这些问题上已经获得了初步有希望的结果，并且正在进行进一步的研究，以增强架构类别的可重构性以及诊断和重构算法的性能。 此外，CAD 和分析工具正在开发中，以协助计算机架构师综合和评估适合提高产量和可靠性的替代高度并行设计。 重点是分析和设计特定于应用程序的可重配置并发架构以及适合 WSI 的重配置算法。