RIA: Integrating Computer-Aided Design and Fault Tolerance for Reconfigurable VLSI/WSI Architectures Design

RIA：集成计算机辅助设计和容错以实现可重构 VLSI/WSI 架构设计

• 批准号: 8908648
• 负责人: Sy-Yen Kuo
• 金额: $ 6万
• 依托单位: University of Arizona
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1989
• 资助国家: 美国
• 起止时间: 1989-06-01 至 1991-11-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8908648&HistoricalAwards=false
• 关键词: RIA; Integrating; Computer; Aided; Design

The objective of this research is to provide an integrated computer- aided design (CAD) environment for the synthesis and evaluation of reconfigurable VLSI (very-large scale integrated) or WSI (wafer-scale integration) concurrent architectures. With the rapid progress of VLSI technology, the chip sizes are to increase substantially, perhaps up to the level of WSI. However, low manufacturing yield has become a problem of increasing significance, especially in WSI where it is unlikely to get a defect-free wafer. Redundancy techniques are being utilized to overcome this difficulty. Substantial yield and reliability improvement in VLSI/WSI parallel architectures can be achieved by a proper integration of the architectural redundancy, fault diagnosis, and reconfiguration techniques. Initial promising results have been obtained on these issues and further investigation is being performed to enhance the reconfigurability of classes of architectures, and performance of diagnosis and reconfiguration algorithms. Moreover, CAD and analysis tools are being developed to assist the computer architect in the synthesis and evaluation of alternative highly parallel designs appropriate for yield and reliability enhancement. The emphasis is on analysis and design of application specific reconfigurable concurrent architectures and reconfiguration algorithms appropriate for WSI.

这项研究的目的是提供一个集成的计算机辅助设计（CAD）环境，以综合和评估可重构VLSI（非常大的量表集成）或WSI（WAFER-SCALE集成）并发体系结构。 随着VLSI技术的快速发展，芯片尺寸将大大增加，也许是WSI的水平。 但是，生产率较低已成为提高意义的问题，尤其是在WSI中，不太可能获得无缺陷的晶片。 冗余技术被用来克服这一困难。 通过正确整合体系结构的冗余，故障诊断和重新配置技术，可以实现VLSI/WSI平行体系结构的大量产量和可靠性提高。 在这些问题上已经获得了最初的有希望的结果，并正在进行进一步的研究，以增强体系结构类别的可重构性以及诊断和重新配置算法的性能。 此外，正在开发CAD和分析工具，以协助计算机架构师综合和评估替代性高度平行设计，适合于产量和可靠性增强。 重点是对应用适用于WSI的特定于应用程序的分析和设计。