Due to the significant process variations, designers have to optimize the statistical performance distribution of nano-scale IC design in most cases. This problem has been investigated for decades under the formulation of stochastic optimization, which minimizes the expected value of a performance metric while assuming that the distribution of process variation is exactly given. This paper rethinks the variation-aware circuit design optimization from a new perspective. First, we discuss the variation shift problem, which means that the actual density function of process variations almost always differs from the given model and is often unknown. Consequently, we propose to formulate the variation-aware circuit design optimization as a distributionally robust optimization problem, which does not require the exact distribution of process variations. By selecting an appropriate uncertainty set for the probability density function of process variations, we solve the shift-aware circuit optimization problem using distributionally robust Bayesian optimization. This method is validated with both a photonic IC and an electronics IC. Our optimized circuits show excellent robustness against variation shifts: the optimized circuit has excellent performance under many possible distributions of process variations that differ from the given statistical model. This work has the potential to enable a new research direction and inspire subsequent research at different levels of the EDA flow under the setting of variation shift.
由于工艺偏差显著,在大多数情况下,设计人员必须优化纳米级集成电路设计的统计性能分布。在随机优化的公式表述下,这个问题已经被研究了数十年,它在假定工艺偏差分布完全已知的情况下,使性能指标的期望值最小化。本文从一个新的视角重新思考了考虑偏差的电路设计优化问题。首先,我们讨论偏差偏移问题,这意味着工艺偏差的实际密度函数几乎总是与给定模型不同,并且通常是未知的。因此,我们建议将考虑偏差的电路设计优化表述为一个分布鲁棒优化问题,它不需要工艺偏差的精确分布。通过为工艺偏差的概率密度函数选择一个合适的不确定性集合,我们使用分布鲁棒贝叶斯优化来解决考虑偏差偏移的电路优化问题。这种方法在一个光子集成电路和一个电子集成电路上都得到了验证。我们优化后的电路对偏差偏移表现出极好的鲁棒性:在许多与给定统计模型不同的工艺偏差可能分布情况下,优化后的电路都具有优异的性能。这项工作有可能开启一个新的研究方向,并在偏差偏移的设定下,激发电子设计自动化流程不同层面的后续研究。